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jan 97 AN90rev1 1 copyright ? crystal semiconductor corporation 1997 (all rights reserved) crystal semiconductor corporation p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http//www.crystal.com AN90 #rystal,!. cs8904 quad 10base-t ethernet transceiver technical reference manual version: 1.0 AN90rev1 january 2, 1997 to obtain technical application support, call (800) 888-5016 (from the us and canada) or 512-442-7555 (from outside the us and canada), and ask for cs8904 application support, or send an email to: ethernet@crystal.cirrus.com
AN90 2 AN90rev1 the information contained in this document is subject to change without notice. crystal semiconductor corporation makes no warranty of any kind with regard to this material including, but not limited to, the implied warranties of mer- chantability and fitness for a particular purpose. crystal semiconductor corporation shall not be liable for errors con- tained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material. this document contains information which is protected by copyright. all rights reserved. no part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of crystal semiconductor corporation. the following are trademarks of crystal semiconductor: streamtransfer, packetpage, and smart analog other trademarks used in this technical reference manual include: ethernet is a registered trademark of xerox corp. other product names may be trademarks of their respective companies.
AN90 AN90rev1 3 table of contents introduction to the cs8904 technical reference manual.....................................................................4 1.0 typical installation ....................................................................................................................4 1.1 evaluation board schematics, bill of materials, and layer plots.......................................4 1.2 crystal oscillator ...............................................................................................................13 1.3 led drivers.......................................................................................................................13 1.4 10base-t interface.............................................................................................................13 2.0 +3 v operation ........................................................................................................................14 3.0 transformer recommendations...............................................................................................14 4.0 using multiple cs8904s with a shared txclk .....................................................................15 5.0 unused ports ............................................................................................................................15 6.0 layout considerations .............................................................................................................15 6.1 clock..................................................................................................................................15 6.2 analog signals ...................................................................................................................15 6.3 digital signals....................................................................................................................16 6.4 power .................................................................................................................................16 list of figures figure 1. port 0 schematic....................................................................................................................4 figure 2. port 1 schematic....................................................................................................................5 figure 3. port 2 schematic....................................................................................................................5 figure 4. port 3 schematic....................................................................................................................6 figure 5. power supply connections ...................................................................................................6 figure 6. header schematic (1 of 2).....................................................................................................6 figure 7. header schematic (2 of 2).....................................................................................................7 figure 8. eeb8904b silkscreen ...........................................................................................................8 figure 9. eeb8904b component side .................................................................................................9 figure 10. eeb8904b ground plane..................................................................................................10 figure 11. eeb8904b power plane....................................................................................................11 figure 12. eeb8904b solder side .....................................................................................................12 figure 13. led circuit .......................................................................................................................13 figure 14. 10base-t interface circuit ................................................................................................14 list of tables table 1. eeb8904 bill of materials .....................................................................................................7 table 2. crystal oscillator requirements...........................................................................................13 table 3. 10base-t components for +5.0v and +3.0v operation ......................................................14 table 4. recommended transformers................................................................................................14
AN90 4 AN90rev1 introduction to the cs8904 technical reference manual this technical reference manual provides infor- mation that will be helpful in designing a board us- ing the cs8904 quad transceiver. it is expected that the user of this technical reference manual will have a general knowledge of hardware design and ethernet. recommended sources of background in- formation are: a) ieee std 802.3u-1995 (iso/iec 8802.3:1996) csma/cd access method and physical layer specifications b) ieee std 802.3u-1995 supplement clause 28 (auto-negotiation) c) ethernet, building a communication infra- structure , by hegering and lapple, addison- wesley, 1993, isbn 0-201-62405-2 d) netware training guide: networking technol- ogies , by debra niedenmiller-chaffis, new riders publishing, isbn 1-56205-363-9 1.0 typical installation this section describes an example cs8904 imple- mentation operating from a +5.0v power supply and using single-port rj-45 connectors and mag- netics. 1.1 evaluation board schematics, bill of materials, and layer plots figures 1 through 7 show the schematic for the cdb8904-1 evaluation board. figures 8 through 12 contain the layer plots of the 4-layer board. ta- ble 1 lists the bill of materials used. figure 1. port 0 schematic
AN90 AN90rev1 5 figure 2. port 1 schematic figure 3. port 2 schematic
AN90 6 AN90rev1 figure 4. port 3 schematic figure 5. power supply connections figure 6. header schematic (1 of 2)
AN90 AN90rev1 7 figure 7. header schematic (2 of 2) * not loaded table 1. eeb8904 bill of materials item reference # description qty vendor part number 1 c5..c15 capacitor, 0.1f, smt 0805, x7r 11 nic nmc0805x7r104k2 2 c22, c29, c35, c42 capacitor, 68pf, c315 4 kemet c315c680j2g5ca 3 c1 capacitor, 22f, t350k 1 kemet t350k226k035as 4 c2, c20, c27, c33, c40 capacitor, 0.1f, c320 5 kemet c320c104k5r5ca 5 r4, r5, r10, r11, r15, r16, r21, r22 resistor, 24.3, 1%, 1/8w, th 8 transohm 271_24.3 6 r2, r3, r8, r9, r13, r14, r19, r20 resistor, 49.9, 1%, 1/8w, th 8 transohm 271_49.9 7 r6, r12, r17, r23 resistor, 680, 5%, 1/8w, th 4 transohm 271_680 8 rn1, rn2 resistor, 4.70k, sip 2 bourns 4606x_101_472 9 r1 resistor, 4.99k, 1%, 1/8w, th 1 transohm 271_4.99k 10 d1..d4 led 4 dialight 561-2201-050 11 y1 crystal, 20.000mhz 1 m-tron ats-49 12 j1..j4 connector, rj45, 8 pin 4 amp 55164-1 13 t1..t4 transformer, 2, 1:1, 1:1.41 - dip 4 halo td42-2006q 14 hdr1..hdr6 header strips 44 amp 4-102973-0 15 j5 banana jacks 1 voltrex 3-881-bk (black) 16 j6 banana jacks 1 voltrex 3-881-r (red) 17 u1 ethernet controller 1 crystal cs8904 * c3, c4, c16, c17 capacitor, 68pf, c315 0 * c18, c19, c21, c23..c26, c28, c30..c32, c34, c36..c39, c41, c43 capacitor, 0.1f, c320 0 * r7, r18 resistor, 0 ohms, th 0
AN90 8 AN90rev1 figure 8. eeb8904b silkscreen
AN90 AN90rev1 9 figure 9. eeb8904b component side
AN90 10 AN90rev1 figure 10. eeb8904b ground plane
AN90 AN90rev1 11 figure 11. eeb8904b power plane
AN90 12 AN90rev1 figure 12. eeb8904b solder side
AN90 AN90rev1 13 1.2 crystal oscillator the clock to the cs8904 can be supplied by either a crystal or an external cmos/ttl clock source. the crystal specifications are given in table 2. the crystal should be connected between xtal1 and xtal2 (pins 38 and 39 respectively) and should be placed as close as possible to the cs8904. if an external clock is used, it should be driven into xtal1 (pin 38), and xtal2 (pin 39) should be left floating (no connection). 1.3 led drivers the cs8904 has 4 led drivers, one per port, to in- dicate link status. these are open-drain outputs. figure 13 shows a typical led implementation. in this example, when a link has been established, the cs8904 led driver turns on, allowing current to flow in the led/resistor chain, thus activing the led. when the link is disconnected, the driver turns off, cutting the current through the led. the use of an led is optional. in systems that re- quire use of the linkledx signal, an external pull-up resistor is required. this signal is active low, that is, the output drives to a low voltage when the link is good. 1.4 10base-t interface figure 14 shows a typical 10base-t interface. transmit and receive lines from the cs8904 are routed to the rj-45 jack through an isolation trans- former. for +5.0v systems, this transformer has a turns ratio of 1:1 between the primary and second- ary windings on the receive side (rx+, rx-) and 1:1.41 between the primary and secondary wind- ings on the transmit side (tx+, tx-). a list of rec- ommended transformers is given in section 3.0. in figure 14, the 0.1f capacitors provide for com- mon-mode filtering on the transmit and receive coils. the rr resistors provide for impedance matching on the receive lines. the rt resistors and the ct capacitor provide impedance matching for the transmit lines. table 2. crystal oscillator requirements parameters min typ max units parallel resonant frequency - 20 - mhz resonant frequency error (c l = 18 pf) -50 - +50 ppm resonant frequency change over operating termperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 35 w +5v linkledx 680 w figure 13. led circuit
AN90 14 AN90rev1 2.0 +3 v operation when the cs8904 is operating from a +3.0v power supply, the 10base-t interface is modified slightly. namely, the turns ratio between the primary and secondary windings on the transmit isolation trans- former must be changed from 1:1.41 to 1:2.5. the turns ratio between the primary and secondary windings on the receive side remain 1:1. addition- ally, the values for the impedance matching com- ponents change as well. these changes are summarized in table 3. table 3. 10base-t components for +5.0v and +3.0v operation 3.0 transformer recommendations table 4 lists manufacturers and part numbers for transformers suitable for use with the cs8904 in +5.0v systems. table 4. recommended transformers rt rt cs8904 td + td - txd + txd - 1 : trt rj45 1 2 1 : trr rd + rd - 3 6 0.1 f + rxd+ rxd- rr rr 0.1 f - ct figure 14. 10base-t interface circuit parameter +5.0 v +3.0 v trt 1:1.41 1:2.5 trr 1:1 1:1 rr 49.9 w 49.9 w rt 24.3 w 8 w ct 68 pf 560 pf vendor cmc? through-hole surface-mount single-port transformers halo n td42-2006q tg42-1406n1 y td43-2006k tg43-1406n pulse n pe-65994 pe-65745 y pe-65998 pe-65746 valor n pt4069 st7011 y pt4068 st7010 quad-port transformers halo n tg44-1406nx y tg46-1406nx pulse n pe-68065 y pe-68062 valor n st4212-1 y st4212-2
AN90 AN90rev1 15 4.0 using multiple cs8904s with a shared txclk when the connecting a set of cs8904s to a mac having a single txclk input, some design consid- erations must be met: 1. all cs8904s must operate from the same clock source. 2. a shared hardware reset signal must be ap- plied to all cs8904's after power-up. 3. the txclk signal should be taken from exact- ly one cs8904 and routed to the txclk input on the media access controller. txclks on the other cs8904's should be left unconnected. 5.0 unused ports ports that are not used in the system (those that have no external rj-45 connection) should be con- figured as follows: 1. loopx should be asserted (polarity depends on mode pins). 2. txenblx should be deasserted (polarity de- pends on mode pins). 3. autoselx, dupselx, and txdatax should all be tied high. 4. tx+/tx- should be left floating (no connec- tion). 5. rx+/rx- should be tied together. 6.0 layout considerations the cs8904 is a mixed-signal device, that is, it im- plements both sensitive analog circuitry and digital control and preprocessing circuitry on a single chip. the mixed-signal nature of the device makes it sensitive to component placement and routing. below is a checklist of guidelines system designers should follow in laying out a printed circuit board. 6.1 clock o if the clock is supplied by an 20 mhz crystal, that crystal should be placed on the component side of the board close to xtal1 and xtal2 (within one inch). crystal traces should be short and should contain no vias. if the clock is supplied by an external cmos/ttl source, the traces should be as short as possible. 6.2 analog signals o the 4.99 k w biasing resistor should be placed close to pins 15 (avss0) and 16 (res). the connection between the biasing resistor and avss0 should be made with a short trace. o the isolation transformers should be placed as close as possible to the rj-45 connectors. if common-mode chokes are employed, they must be placed on the rj-45 side of the iso- lation transformers. o traces in the 10base-t signal path, those lead- ing from rx+/rx-, tx+/tx- on the cs8904 through the isolation transformer and out to the rj-45 jack, should be direct and short. the trace width on the receive traces should be at least 25 mills (50 w characteristic impedance at 10 mhz) and the trace width on the transmit traces should be at least 100 mills wide (25 w characteristic impedance at 10 mhz). particular care should be taken to match the characteristic impedance of each transmit trace to the value of rt (in figure 14). for a +5.0v, 2-layer board using fr-4 laminate with a thick- ness of 0.0625, two 100 mill traces w/ ground plane underneath yield a characteristic imped- ance that approximately matches rt. o route each differential signal pair for the trans- mit lines and the receive lines adjacently. for example, the trace leading from rx+ should be routed parallel to the trace leading from rx-. additionally, special care should be taken to ensure that these traces have the same length. o add either "ground shield" traces or use ground
AN90 16 AN90rev1 plane fill around each transmitter's differential signal pair. for example, the traces gnd, tx+, tx-, gnd, form a shielded differential signal pair. if the ground shield traces are used, they should be stitched, or tied to the groundplane periodically along their length. figure 9 shows an example of using ground shielding traces on the transmit lines. the use of ground plane fill on all trace layers is strongly recommended. 6.3 digital signals o digital signals, particularly the mac data sig- nals (rxclk, rxdata, cd, txclk, txda- ta, txenbl), should not be routed under the cs8904 and should be kept as far as possible from the analog traces. 6.4 power o each power supply pin should be decoupled by its own small-valued (0.1f or 0.01f) decou- pling capacitor. each of these capacitors should be placed as close as possible to the power supply pins they decouple. power sup- ply traces, as well as traces to the decoupling capacitors, should typically be as wide as pos- sible

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